Methods and systems for providing visual display are known in the art. One technique for providing visual display is called Active-Matrix Liquid-Crystal Display (AMLCD) in which each pixel includes a display element (e.g., liquid crystal) a memory storage for retaining the electrical state of that pixel and a transistor for setting that electrical state.
Reference is now made to FIGS. 1A, 1B, 10 and 1D. FIG. 1A is a schematic illustration of a conventional AMLCD display, generally referenced 10, which is known in the art. FIGS. 1B and 1C are schematic illustrations of a single electrical potential setting section, generally referenced 24AR of display 10 of FIG. 1A, which is known in the art, at different states. FIG. 1D is a schematic illustration of a specific implementation of a sub-pixel, generally referenced 22AR, of display 10 of FIG. 1A, which is known in the art.
Display 10 includes a plurality of pixels 20A, 20B, 20C and 20D. Each of pixels 20A, 20B, 20C and 20D includes three respective sub-pixels 22AR, 22AG, 22AB, 22BR, 22BG, 22BB, 22CR, 22CG, 22CB, 22DR, 22DR and 22DB. It is noted that a typical display such as display 10, may contain any number of pixels, from a few thousands and up to several millions and more, and that FIG. 1A, provides a mere illustration of a very small portion of a typical display. Each of sub-pixels 22AR, 22AG, 22AB, 22BR, 22BG, 22BB, 22CR, 22CG, 22CB, 22DR, 22DG and 22DB includes a liquid crystal section directed at a predetermined wavelength range such as Red (R), Green (G) and blue (B), a respective capacitor (not shown) and further a respective electrical potential setting section referenced 24AR, 24AG, 24AB, 24BR, 24BG, 24BB, 24CR, 24CG, 24CB, 24DR, 24DG and 24DB. Display 10 further includes a select driver 12 and a data driver 14. Select driver 12 is coupled to each of electrical potential setting sections 24AR, 24AG, 24AB, 24BR, 24BG and 24BB via select line 181 and further to electrical potential setting sections 24CR, 24CG, 24CB, 24DR, 24DG and 24DB via select line 182. Data driver 14 is coupled to each electrical potential setting sections 24AR and 24CR via data line 161R, to each electrical potential setting sections 24AG and 24CG via data line 161G, to each electrical potential setting sections 24AB and 24CB via data line 161B, to each electrical potential setting sections 24BR and 24DR via data line 162R, to each electrical potential setting sections 24BG and 24DG via data line 162G and to each electrical potential setting sections 24BB and 24DB via data line 162B.
With reference to FIG. 1B, electrical potential setting section 24AR includes a switch 30. Switch 30 is coupled with a capacitor 32, select line 181 and data line 161R. Select line 181 controls the state of switch 30 to be either open (as shown in FIG. 1B) or closed (as shown in FIG. 1C). Data line 161R sets to a certain potential V1, respective with a desired state of transmittance (e.g., transparent, opaque or various levels of semi-transparency), for the respective LCD layer (not shown). In FIG. 1B, capacitor 32 exhibits a potential V0, wherein V0≠V1. In FIG. 10, select line 181 changes the state of switch 30 from open to closed, thereby coupling data line 161R with capacitor 32 and setting capacitor 32 to exhibit potential V1. Capacitor 32 induces this potential V1 on to the respective LCD layer which in turn is set to the desired state of transmittance.
With reference to FIG. 1D, switch 30 is implemented in the form of a transistor 33, having a gate electrode 36, a drain electrode 34 and a source electrode 38. Gate electrode 36 is coupled with select line 181, source electrode 38 is coupled with data line 161R and drain electrode 34 is coupled with capacitor 32 and further with LCD element R of sub-pixel 24AR. Select line 181 controls the state of the transistor 33, in time to alternately be in either an open state, a closed/conductive state, a resistive state (i.e., partially/semi-conductive) and the like, coupling between date line 181 and capacitor 32.
Reference is further made to FIG. 1E, which is a schematic illustration of an electrical potential setting section, generally referenced 44, which is known in the art. Electrical potential setting section 44 includes two switches 40A and 40B. Each one of switches 40A and 40B is coupled with a capacitor 42, and further with LCD element R of a sub-pixel (not shown), a select line 48 and to a data line 46. Select line 48 operates switches 40A and 40B to simultaneously be in the same state, which is either an open state or a closed state. Data line 46 simultaneously sets a potential level V1 at one end of switches 40A and 40B. Once select line 48 sets switches 40A and 40B to the closed state, 40A and 40B connect data line 48 to capacitor 42, thereby charging capacitor 42 to potential level V1′ and setting it to that potential level.
U.S. Pat. No. 8,832,748 to Bushell et al, entitled “Apparatus for aircraft dual channel display” directs to a display, which includes a pixel matrix, back light illumination and two video channels capable of displaying a video signal on the display panel. Each video channel includes respective column drivers, row drivers, LED drivers, timing controller, backlight controller, and a power source. The column and row drives of each channel couples to the columns and rows in the pixel matrix, such as a liquid crystal matrix and drives electrically isolated, interleaved color groups within each pixel. A switch provides for selecting between the two independent video channels to display a video signal on the display. In the display directed to by Bushell et al, each pixel includes two or four color groups of subpixels each group includes a red, a green and a blue subpixel. Each channel drives one color group or a pair of color groups. Such a configuration may provide even distribution of active subpixels upon failure of one of the channels.